Conventional semiconductor wafers are produced in a multiplicity of successive process steps, which can generally be subdivided into the following groups:    a) production of a single crystal composed of semiconductor material (crystal pulling);    b) separation of the semiconductor single crystal into individual wafers (“wafering”, “sawing”);    c) mechanical processing of the semiconductor wafers;    d) chemical processing of the semiconductor wafers;    e) chemomechanical processing of the semiconductor wafers;    f) thermal treatment of the semiconductor wafers and/or epitaxial coating of the semiconductor wafers.
In addition there are a multiplicity of secondary steps such as cleaning, measuring and packaging.
A semiconductor single crystal is usually produced by pulling a single crystal from a melt (CZ or “Czochralski” method) or by recrystallizing a rod composed of polycrystalline semiconductor material (FZ or “floating zone” method).
Known separation methods include wire sawing (“multi-wire slicing”, MWS) and internal-diameter sawing.
In the case of wire sawing, a multiplicity of semiconductor wafers are sliced from a piece of crystal in one work operation.
The mechanical processing serves for removing sawing undulations, for removing the surface layers that were damaged in crystalline fashion by the rougher sawing processes or were contaminated by the sawing wire, and primarily for global leveling of the semiconductor wafers. Surface grinding (single-side, double-side) and lapping are used here, and also mechanical edge processing steps.
In the case of single-side grinding, the semiconductor wafer is held on the rear side on a support (“chuck”) and leveled on the front side by a cup grinding disk with rotation of support and grinding disk and slow radial advance. Methods and apparatuses for the surface grinding of a semiconductor wafer are described in U.S. Pat. Nos. 3,905,162 and 5,400,548 or EP-0955126, for example, each of which is incorporated by reference herein. In this case, a semiconductor wafer is fixedly held on a wafer holder by one of its surfaces, while its opposite surface is processed by means of a grinding disk, by wafer holder and grinding disk rotating and being pressed against one another. In this case, the semiconductor wafer is fixed on the wafer holder in such a way that its center substantially corresponds to the rotation center of the wafer holder. Moreover, the grinding disk is positioned in such a way that the rotation center of the semiconductor wafer reaches a working region or the edge region formed by teeth of the grinding disk. As a result, the entire surface of the semiconductor wafer can be ground without any movement in the grinding plane.
In the case of simultaneous double-side grinding (“double-disk grinding”, DDG), the semiconductor wafer is simultaneously processed on both sides in a manner floating freely between two grinding disks mounted on opposite collinear spindles, and in the process is guided in a manner largely free of constraining forces axially between a water cushion (hydrostatic principle) or air cushion (aerostatic principle) acting on the front and rear sides, and is prevented from floating away radially loosely by a surrounding thin guide ring or by individual radial spokes.
In the case of lapping, the semiconductor wafers are moved under a specific pressure with supply of a slurry containing abrasive materials between an upper and a lower working disk, which are usually composed of steel and normally provided with channels for better distribution of the lapping agent, whereby semiconductor material is removed.
DE 103 44 602 A1 and DE 10 2006 032 455 A1, which are incorporated by reference herein describe methods for the simultaneous grinding at the same time of both sides of a plurality of semiconductor wafers with a movement sequence similar to that of lapping, but characterized by the fact that abrasive is used which is fixedly bonded in working layers (“films”, “pads”) applied to the working disks. A method of this type is referred to as “fine grinding with lapping kinematics” or “planetary pad grinding” (PPG).
Working layers which are used in the case of PPG and which are adhesively bonded onto the two working disks are described for example in U.S. Pat. Nos. 6,007,407 A and 6,599,177 B2, which are incorporated by reference herein. During processing, the semiconductor wafers are inserted into thin guide cages, so-called carriers, which have corresponding openings for receiving semiconductor wafers. The carriers have an outer toothing which engages into a rolling apparatus comprising inner and outer toothed rings and are moved by means of said rolling apparatus in the working gap formed between upper and lower working disks.
The edge of the semiconductor wafer including any existing mechanical markings such as an orientation notch is usually processed as well (“edge rounding”, “edge notch grinding”). Conventional grinding steps with profiled grinding disks or belt grinding methods with continuous or periodic tool advance are used for this purpose.
These edge rounding methods are usually provided since the edge in the unprocessed state is particularly fracture-sensitive and the semiconductor wafer can be damaged even by slight pressure and/or temperature loads in the edge region.
The wafer edge that has been ground and treated with an etching medium is usually polished in a later processing step. In this case, the edge of a centrally rotating semiconductor wafer is pressed against a centrally rotating polishing drum with a specific force (contact pressure). U.S. Pat. No. 5,989,105, which is incorporated by reference herein describes an edge polishing method of this type wherein the polishing drum is composed of an aluminum alloy and has a polishing pad applied to it. The semiconductor wafer is usually fixed on a flat wafer holder, a so-called chuck. The edge of the semiconductor wafer projects beyond the chuck, such that it is freely accessible for the polishing drum.
The group of chemical processing steps usually comprises wet-chemical cleaning and/or etching steps.
The group of chemomechanical processing steps comprises polishing steps by which, through in part chemical reaction and in part mechanical material removal (abrasion), the surface is smoothed and residual damage of the surface is removed.
While the polishing methods that work on one side (“single-side polishing”) generally lead to poorer plane-parallelisms, polishing methods acting on both sides (“double-side polishing”) make it possible to produce semiconductor wafers having improved flatness.
After the grinding, cleaning and etching steps, in accordance with conventional methods, the surface of the semiconductor wafers is smoothed by stock removal polishing. In the case of single-side polishing (SSP), semiconductor wafers are held on the rear side on a support plate by means of cement, by vacuum or by means of adhesion during processing. In the case of double-side polishing (DSP), semiconductor wafers are loosely inserted into a thin toothed disk and polished on the front and rear sides simultaneously in “freely floating” fashion between an upper and a lower polishing plate covered with a polishing pad.
Furthermore, the front sides of the semiconductor wafers are often polished in haze-free fashion, for example by means of a soft polishing pad with the aid of an alkaline polishing sol. This step is often referred to as CMP polishing (“chemomechanical polishing”) in the literature. CMP methods are described, for example, in US 2002-0077039 and in US 2008-0305722, which are incorporated by reference herein.
Conventional methods may also include the so-called “fixed abrasive polishing” (FAP) technologies, wherein the silicon wafer is polished on a polishing pad which, however, contains an abrasive material bonded in the polishing pad (“fixed-abrasive pad”). A polishing step in which such an FAP polishing pad is used is hereinafter referred to for short as FAP step.
WO 99/55491 A1, which is incorporated by reference herein, describes a two-stage polishing method, comprising a first FAP polishing step and a subsequent second CMP polishing step. In CMP, the polishing pad contains no bonded abrasive material. Here, as in the case of a DSP step, abrasive material is introduced in the form of a slurry between the silicon wafer and the polishing pad. Such a two-stage polishing method is used, in particular, to eliminate scratches left by the FAP step on the polished surface of the substrate.
The German patent application DE 102 007 035 266 A1, which is incorporated by reference herein, describes a method for polishing a substrate composed of silicon material, comprising two polishing steps of the FAP type, which differ in that in one polishing step a polishing agent slurry containing unbonded abrasive material as solid is introduced between the substrate and the polishing pad, while in the second polishing step the polishing agent slurry is replaced by a polishing agent solution that is free of solids.
Semiconductor wafers are often provided with an epitaxial layer, that is to say with a layer grown in monocrystalline fashion and having the same crystal orientation, on which semiconductor components are applied later. Such epitaxially coated semiconductor wafers have certain advantages over semiconductor wafers composed of homogeneous material, for example the prevention of charge reversal in bipolar CMOS circuits followed by the short circuit of the component (“latch-up” problem), lower defect densities (for example reduced number of COPs (“crystal-originated particles”)) and the absence of an appreciable oxygen content, whereby it is possible to rule out a short-circuit risk owing to oxygen precipitates in component-relevant regions.
What is important is how the above-described mechanical and chemomechanical or purely chemical method steps are arranged in a process sequence for producing a semiconductor wafer.
It is known that the conventional polishing steps such as SSP, DSP and CMP, the etching treatments and the epitaxy step lead to a deterioration in the flatness of the semiconductor wafer particularly in the edge region.
Endeavors have been made to minimize the material removal during polishing, in order also to limit the deterioration in flatness to a minimum.
For this purpose, it has been proposed, for example, to introduce a fine grinding step. Fine grinding means that grinding tools with finer granulation than in the case of DDG are used.
The advantages of such fine grinding are described in DE 10 2005 012 446 A1, which is incorporated by reference herein. The material removals during etching and polishing can be reduced by means of fine grinding. This makes it possible to prevent the good geometry after the grinding steps such as DDG or PPG from being overly impaired by subsequent etching and polishing.
However, the nanotopography of the semiconductor wafer also plays an important part. The nanotopography can be expressed for example as a height fluctuation PV (=“peak to valley”), relative to square measurement windows having an area of 2 mm×2 mm.
The Nanomapper® instrument from KLA Tencor is often used for examining the nanotopography.
This interferometer is suitable for measuring the topography in the range of from −20 nm to +20 nm on the front side of a semiconductor wafer. During the measurements, the semiconductor wafer is situated on a soft, flat wafer holder (chuck). The resulting peak-to-valley (PV) values are filtered (Gaussian high-pass filter) and analyzed on circles with a diameter of 2 mm (additionally also on circles with a diameter of 10 mm) with respect to peak-to-valley deviations. In the THA (“threshold height analysis”) analysis, for details see SEMI standard M43, the three sigma PV value is finally calculated from the distribution of all the PV values as a so-called THA value.
The THA values are often also referred to as THA-2 mm or THA-10 mm in order to indicate the size of the analysis windows. It has been found that although fine grinding allows smaller etching and polishing removals, it has an adverse influence on the THA-2 mm value, that is to say is associated with an impairment of the shorter-wave nanotopography.
Such topography differences also often occur in the form of so-called striations. These striations can be attributed to fluctuations in the dopant concentrations. These striated structures become apparent after chemical or chemomechanical processing steps.
In the German patent application bearing the file reference 102009030296.4, not previously published, which is incorporated by reference herein, it is indicated that the FAP-polishing could afford advantages in this regard.
Finally, the edge geometry of the semiconductor wafers is also important. In order to make even the outermost edge region of the semiconductor wafer accessible to the modern lithographic methods (immersion lithography), improvements in the edge geometry are indispensable. It has been suggested that conventional DSP polishing, in particular with respect to the new generation of 450 mm wafers, should be replaced in this regard by new polishing methods.